Generally, desired semiconductor devices are manufactured by repetitively performing various processes such as film formation, pattern etching and the like on a semiconductor wafer. Meanwhile, in order to meet demand for higher integration and higher miniaturization of semiconductor devices, a line width or a hole diameter is getting gradually miniaturized. As for a wiring material or a burying material to be buried in a recess such as a trench, a hole or the like, copper having a very low electrical resistance and a low price tends to be used to reduce an electrical resistance in accordance with the miniaturization of various dimensions (see Japanese Patent Application Publication No. 2004-107747). When copper is used for a wiring material or a burying material, generally, a tantalum (Ta) metal or a tantalum nitride (TaN) film or the like is used for a barrier layer.
In order to fill the recess with copper, first, a thin seed layer made of a copper film is formed on an entire wafer surface including an entire wall surface in the recess in a plasma sputtering apparatus. Next, the recess is completely filled with copper by performing a copper plating process on the entire wafer surface. Thereafter, a residual copper thin film on the wafer surface is removed by polishing such as a CMP (chemical mechanical polishing) process or the like.
This will be described with reference to FIGS. 7A to 7C. FIGS. 7A to 7C show conventional processes for burying a recess of a semiconductor wafer. On a surface of an insulating layer 1 formed of an interlayer insulating film, e.g., an SiO2 film, which is formed on the semiconductor wafer W, a recess 2 corresponding to, e.g., a via hole, a through hole or a groove (trench) is formed by a single damascene structure, a dual damascene structure, a three-dimension mounting structure or the like. Accordingly, a lower wiring layer 3 formed of a metal film, e.g., a copper film, is exposed at a bottom portion of the recess.
Specifically, the recess 2 includes a thin and long groove (trench) 2A having a recess-shaped cross section and a hole 2B formed at a part of a bottom portion of the groove 2A. The hole 2B is a via hole or a through hole. The wiring layer 3 is exposed to a bottom portion of the hole 2B, and is electrically connected to an underlying wiring layer or an element such as a transistor or the like. Illustration of the underlying wiring layer or the element such as the transistor or the like is omitted. The recess 2 has a very small width or inner diameter such as about 120 nm in order to meet a scaling-down requirement of a design rule. An aspect ratio thereof is required to be, e.g., about 2 to about 4. Illustration of a diffusion barrier layer and an etching stop film is omitted, and a simple shape is shown in the drawings.
On the surface of this semiconductor wafer W which includes the inner surface of the recess 2, a barrier layer 4 including, e.g., a TaN film and a Ta film in a laminated structure is substantially uniformly pre-formed by a plasma sputtering apparatus (see FIG. 7A). Then, a seed film 6, made of a thin copper film, as a metal film is formed over the entire surface of the wafer including the inner surface of the recess 2 by the plasma sputtering apparatus (see FIG. 7B). By performing a copper plating process on the surface of the wafer, the inside of the recess 2 is filled with a metal film 8 such as a copper film (see FIG. 7C). Thereafter, remnants of the metal film 8, the seed film 6 and the barrier layer 4 on the wafer surface are polished and removed by the CMP or the like.
In order to increase reliability of the barrier layer, various developments have been made. Particularly, attention is given to a self-forming barrier layer using a Mn film or a CuMn alloy film instead of using the Ta film or the TaN film (see Japanese Patent Application Publication No. 2005-277390). The Mn film or the CuMn alloy film is formed by sputtering. Further, the Mn film or the CuMn alloy film itself serves as a seed film. Thus, a Cu plating layer can be directly formed thereon. Moreover, by performing annealing after the plating, the Mn film or the CuMn alloy film reacts with a SiO2 layer as an underlying insulating film by self-alignment. Accordingly, a MnSixOy film (x, y: a positive number) or a manganese oxide (MnOx) film (x: a positive number) formed by a reaction between Mn and oxygen in the SiO2 layer is formed as a barrier layer at a boundary between the SiO2 layer and the Mn film or between the SiO2 layer and the CuMn alloy film. As a result, the number of processes can be reduced. The manganese oxide includes, e.g., MnO, Mn3O4, Mn2O3, and MnO2 depending on a valency of Mn. In this specification, these oxides are generally referred to as “MnOx”. Furthermore, this will be applied to TaOx to be described later.
Further, there has been discussed that a MnSixOy film or a MnOx film is formed by a CVD method capable of forming a film having a fine line width or a fine hole diameter with a good step coverage as compared with the sputtering method (see Japanese Patent Application Publication No. 2008-013848).
Recently, in order to meet demand for a higher operation speed of semiconductor devices, the interlayer insulating film needs to have a lower relative permittivity. Due to this demand, there has been considered to use a low-k film formed of SiOC, SiCOH or the like containing an organic group, e.g., a methyl group or the like, and having a lower relative permittivity as a material of the interlayer insulating film, instead of a silicon oxide film made of TEOS. Here, the silicon oxide film formed by using the TEOS has a relative permittivity of about 4.1, whereas the low-k film made of SiOC has a relative permittivity of about 3.0.
However, when the material having a low relative permittivity such as the low-k film (SiOC) is used as the interlayer insulating film, a MnOx film is hardly formed on a surface of the interlayer insulating film having a low relative permittivity as well as an exposed surface in the recess even if a process for forming a Mn-containing film is performed by CVD. Thus, a barrier layer cannot be formed thereon.